Non-volatile memories (NVMs) have a major role in current semiconductor products either as stand alone devices or embedded applications such as onboard a chip having logic. A large percentage of microcontrollers include such an NVM. There are many applications where it is sufficient or at least beneficial to be able to erase an entire NVM array or subarray in a single operation. This operation is often called block erase. Typically such NVMs have a floating gate for each memory device. An alternative becoming available is using nanocrystals which results in many very small floating gates per memory cell. In either case a problem with block erase is that high voltages are required; higher than required for programming. These high voltages require special generation with specially made transistors that can support these higher erase voltages. To reduce the requirement of special high voltage transistors, erase voltage is split between the control gate of the memory cell and its channel. This requires a body contact which requires significant additional space and special processing in a semiconductor-on-insulator (SOI) substrate, which is becoming preferable to bulk silicon substrates for higher performance and lower power logic. Another problem for one time programmable (OTP) memories is that of process induced charging during processing of the overlying interconnect. This occurs for non-OTP memories as well but block erase is readily available for them. For OTP memories the processing induced charging is removed by ultra-violet (UV) erase but this is becoming more difficult to achieve because of the increased interconnect density and the dielectric materials being used. For example, silicon carbon nitride, which does not transmit UV well, may become one part of the dielectric used in the interconnect. In such a situation OTP memories may not be practical.
Thus, there is a need for improving one or more of these difficulties in erasing an NVM.